Perl, Verilog, Python, Synopsys VCS, Cadence Incisive, VHDL, Modelsim, Uvm

Python, Jasper VC, Formal Questa, Formal 360-DV, Formal verification tools

C, Bash, Perl, Verilog, Python, Tcl, IP architecture, Debug, stimulus development, verification planning, Digital Design, Uvm, systemverilog, scoreboards, assertions, functional coverage

wireless protocols , modem, System Verilog, Wifi Standards, constraint random tests, assertion coverage-based verification methodology, debugging RTL TB issues using Verdi, Uvm, formal static verification methodologies

Verilog, Sata, Python, Perl, Usb, Uvm, constrained random verification, functional coverage, PCI Express, systemverilog, VMM, DV methodologies

protocol stack , Java, Lte, Python, Bash, Jenkins, Git, Gerrit, ip networking, air-interface technologies, CI CD concepts, Troubleshooting, performance verification, 5G NR, Linux environments, system-level verification, RAN architecture