System Verilog, Building test benches from scratch, Data path verification performance tests, Gate level simulation, ASIC verification using UVM, formal verification

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, UCIe, Uvm, systemverilog, AMBA, Axi

Golang, Google Cloud Platform, Python, Sql, GenAI models, Google BigQuery

Dsp, C, Java, Os, Firmware, Automation, Python, PSR, Driver, Display Validation, DPU, Hardware, FHD, Type-C, HDCP, Multi-display, VRR, HDR, 4K, 2K, Dsc, USB4, HDMI

Excel, Python, Ms Word

System Verilog, Building test benches from scratch, ASIC verification using UVM

spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, multi-domain clock synchronization, high performance memory subsystems, ASIC debugging

power supplies , C, I2c, Python, Labview, Automation of Equipment and Tests, SVI3, scopes, Relays, ATE programs, PMBUS, Computer to IC board communications, Basic circuits on bread board, SVID, Probes, SPMI, Power Chip Communication protocols, Validation related equipment, Load Slammer, FPGAs, Multi-meters, Bench Validation, Debug of Power Management ICs, Design PCBs, Analog switches

Unix, Python, Lsf, Bitbucket, Static timing analysis, AI ML, Jenkins, Git, Linux, Splunk, GenAI, CI CD process, DesignSync, Dft, EDA Tools, ASIC Design, Convolutional Networks, Graph Neural Networks, VLSI CAD, make, reinforcement learning, Design revision control, Design Verification, Power-aware flows