System Verilog, Building test benches from scratch, ASIC verification using UVM

Vcs, Pcie, Python, Perl, Ethernet, Tcl, Xcelium, Uvm, Testbench Architecture, LPDDR4, Functional Coverage, Verdi, UCIe, systemverilog, Axi, MIPI, Constrained Random Verification, APB, DVE, USB4, USB3, Questa, CXL, DDR5, DDR4, AHB, SVA

code coverage , Vcs, Nlp, Test Plan Creation, verification closure, UVM methodology, non-NLP simulations, VS Code, systemverilog, GLS, GitHub CoPilot, debugging of complex mixed signal designs, testbench architecture, verification of mixed signal IP Design, Git version control, constraint-random test generation, failure root cause analysis, waveform debugs, functional coverage

Soc Architecture, System Verilog, digital design concepts, UVM Universal Verification Methodology, debugging using waveforms and logs

Test Case Creation, Shell, Perl, Python, Advanced Debugging skills, Uvm, testbench development, coverage-driven verification, Computer Architecture concepts, Formal Verification techniques, Functional Verification, Rtl Design

Design Verification, Uvm, Verification Planning, systemverilog

C++, Usb, Ethernet, Perl, engineering services, Asic verification

Usb, Fpga, Perl, Pcie, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, MIPI, formal verification, test bench infrastructure, transaction level modeling, AXI4

Usb, Fpga, Soc Architecture, Pcie, Perl, Debugging, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, AMBA, formal verification, Test Bench, transaction level modeling, AXI4

Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, Post-silicon debugging, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming