Meet The Team

The Common Hardware Group (CHG) delivers silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.

Your Impact

You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification.
Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design
Collaborate with the design/design-verification and PD teams to enable the integration and validation of the test logic in all phases of the implementation and post silicon validation flows.
Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug methodologies and standards.
The job requires the candidate to have the ability to craft solutions and debug efficiently.
Mentor and guide DFT DV engineers and provide technical leadership across projects.

Minimum Qualifications

Bachelor's or master's degree in electrical or computer engineering required with at least 10+ years of experience.
Experience in developing detailed test plans and test benches for DFT verification
Prior experience in test planning based on complex design specifications.
Prior experience in testbench development using System Verilog.
Debugging experience using DVE/Verdi.
Scripting skills: Tcl, Python/Perl.

Preferred Qualifications

UVM and advanced System Verilog knowledge.
Knowledge about JTAG protocol, scan architecture, MBIST and boundary scan.

Why Cisco

At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

ASIC DFT DV Technical Lead