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Showing 4 jobs
Skills:
Verilog, System Verilog, Synopsys VCS, Cadence IES, formal property checking tools, Uvm
Skills:
Verilog, Ovm, System Verilog, Synopsys VCS, Cadence IES, VMM, formal property checking tools, Uvm
Skills:
Usb, C, C++, Debugging, Test Plan, Object Oriented Programming, Writing Test Cases, Oop, DDR, Ethernet, Pcie, Perl, Tcl, Function coverage, Coverage driven verification, Uvm, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, CXL, Test bench development, Simulation, System-Verilog
Skills:
Verilog, systemverilog, Digital and analog simulation tools, Uvm, PrimeSim, Verification strategy, Design Verification, Hspice, FineSim
