FinFET GAA layout concepts, Cadence Virtuoso Custom Layout, Calibre PVS, advanced-node analog custom layout, PEX, parasitic optimization, physical verification flows, post-layout simulation correlation, matching shielding guard rings isolation

reliability driven layout practices, Calibre, analog mixed-signal IC layout, PEX, DRC, parasitic-aware layout, antenna rules, post-layout simulation correlation, LVS, Cadence Virtuoso

Routing, Pvs, PERL, Tcl, R3D, PEX, LVS, Layout Techniques, Verification, Skill Programming, CAD Tools, Calibre, Analog Layout, ERC, VCAR, DRC, VSR, virtuoso