Shell, Verilog, Unix, C, Python, Perl, Linux, Uvm, systemverilog

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, AMBA, Axi, UCIe, systemverilog

DDR, Pcie, Perl, Ethernet, Python, Design Verification, Uvm, emulation environments, RTL Verilog, HBM, SoC IP, high-speed protocols, AI ML SoCs

redhawk , Scripting, Tcl, Perl, routing, Shell, Python, floorplanning, Physical Verification, variability analysis, EDA Tools, EM, Ir, Placement, primetime, Synopsys ICC2, Cadence Innovus, CTS, low-power design, automation skills, Voltus, Si, Timing Closure, ASIC SOC physical design implementation, StarRC

automation, Scripting, Static Timing Analysis, Python, AHB, Synthesis, LINT, EDA Tools, frontend flows, memory interfaces, standard interface protocols, SoC-level integration, cdc, Memory Controller IPs, Rtl Design, Safety Security and Debug architectures, Interconnect Fabrics, formal verification techniques, static dynamic power checks, Axi, Dft, ARM Cores

Tcl, FPGA Design, System Verilog, C, Python, Unix Shell Script, Perl, Vcs, Synthesis, RTL validation, LINT, Synopsys simulators

static timing analysis, Python, Perl, LINT, digital IC ASIC design, RTL quality tools such as Spyglass, cdc, RTL design using Verilog, VHDL, EDA tools for synthesis, RDC, low-power design techniques, Simulation