Software Release Management, Shell scripting, Deployment Git, WLAN standards IEEE 802.11, Automation using Python

Shell, Perl, Python, Synopsys VCS, Siemens Questa, Cadence Xcelium, CPF, Uvm, UPF, systemverilog, SVA

Python, FineSim, Synopsys VCS, Skill, Xcelium, Verilog-AMS, SystemVerilog-RNM, Cadence Virtuoso, Spectre

UFS (Universal Flash Storage), C, C++, Makefile, Perl, Verilog, Ethernet, System Verilog, Verification tools such as VCS, System Verilog verification language, Uvm, Synopsys VIPs, Waveform analyzer, Asic Design Verification, ASIC flow, AXI-AMBA protocol variants, PCIe Protocol

Arm, Python, RTL simulation, Debug, functional coverage closure, RISC-V, regression automation, x86 architecture, Uvm, SVA, systemverilog

Bus protocols - APB, C, Usb, Uart, Spi, Test Plan Creation, Pcie, I2c, System Verilog, Bus interconnects, Checkers, i2s, Uvm, Functional coverage, DP, Sd, AHB, Verification methodology, Gate-level simulations, Scoreboards, Gate Level Power-Aware simulations, Axi