Arm, SoC architectures, formal verification, RTL fundamentals, Digital Design, Uvm, RISC, systemverilog

Systemc, Test Planning, C, Shell, Tcl, Verilog, Python, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, constrained-random verification, formal verification, power-aware verification

Verilog, System Verilog, LPDDR, Uvm, DDR memory protocols, HBM, Functional Verification

embedded software programming , C, Python, Pcie, DDR, SoC Verification, Uvm, ARM-based SoCs, system-level test generation, systemverilog, Emulation, reusable verification libraries, virtual platforms, Portable Stimulus PSS, constrained-random verification, Perspec, post-silicon validation, verification methodology

Tcl, Python, Shell, Soc Architecture, Rtl Design, UVM verification flows, Linux environments, Siemens Veloce, Synopsys ZeBu, systemverilog