Soc Architecture, System Verilog, digital design concepts, UVM Universal Verification Methodology, debugging using waveforms and logs

Perl, Shell scripting, Python, Low Power Verification UPF CPF, AMBA AXI AHB APB, USB 2.0 3.x, ARM-based SoCs, SystemVerilog UVM

Ovm, System Verilog, Uvm, constrained random verification methodologies, FPGA prototyping, FPGA architecture, Pre Silicon Validation Verification

Test Case Creation, Shell, Perl, Python, Advanced Debugging skills, Uvm, testbench development, coverage-driven verification, Computer Architecture concepts, Formal Verification techniques, Functional Verification, Rtl Design

hardware engineering , Vcs, Perl, Python, Xcellium, NCSim, Uvm, UPF, systemverilog, Low power verification, Gate level simulation, VCFormal, Questa, Jaspergold, Functional Verification, Modelsim, formal verification

Jenkins, Verilog, Makefile, Python, Functional Coverage, Uvm, systemverilog