Usb, Pcie, Perl, Verilog, Python, Makefiles, RTL Build flows, AMBA protocols, Debug architecture, Axi, SoC Clocks, SDCC, APB, RST, SOC design, AHB, System-Verilog

C, Gdb, Verilog, Scripting Languages, Python, Indago, Micro-Architecture, Cadence, SOC development, Physical Design, Rtl Design, Timing Closure, Verification, ASIC architecture

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation