cache coherency , Noc, Pcie, Verilog, Clearcase, Python, Git, Perl, Tcl, architecture definition, RTL implementation, cdc, Infrastructure IPs, custom protocol design, RDC, memory systems, microarchitecture development, Synthesis, UALink, ESUN, AI scale-up interconnect fabrics, systemverilog, LINT, Timing Closure, performance optimization, CXL

C, Vcs, Jtag, Perl, Verilog, Python, Tcl, Verdi, MBIST, DFT micro-architecture, Synopsys Tetramax, EDA Tools, Scan, Mentor Tessent

static timing analysis, Perl, Python, EDA tools for synthesis, LINT, cdc, digital design principles, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, RTL quality tools such as Spyglass, RDC, VHDL, low-power design techniques

arm architecture , Uart, Pcie, Verilog, I2c, Flash, low power methodology, system debug infrastructure, RTL level checks, digital ASIC design, systemverilog, SSP, AMBA bus protocols, system memory hierarchy, constraints development, ARM based ecosystem components, multi-core SOC designs, DRAM, ARM v8 and v9 specifications, DC DC-T based synthesis

Unix, Lsf, Jenkins, Git, Shell, Linux, Verilog, Gitlab, Python, Tcl, Synthesis, cdc, Simulation, RTL, make, systemverilog, RDC, UGE, LINT, Low Power, Slurm