Perl, Python, constraint-random testing, Power-aware verification, formal static verification techniques, coverage-driven verification methodologies, Uvm, systemverilog

Verilog, Pcie, SVA, formal verification, Assertions, Uvm, interconnect protocols, debugging complex RTL, systemverilog, CHI, AHB, Functional verification methodologies, Axi, testbench issues, Coverage

Verilog, Sata, Python, Perl, Usb, VMM, constrained random verification, Uvm, functional coverage, PCI Express, systemverilog, DV methodologies