PERL, Tcl, Sta, Synthesis, CTS, Place Route, Full-chip Floor-planning, RTL2GDSII flow, ICC2, Physical Verification, Tempus, Make scripting, layout closure, timing convergence, primetime, Innovus, Physical Design, Timing Closure, high frequency design methodologies

Soc, PD convergence, PV fixing, ASIC Design, scripting with TCL, EMIR fixing, Vlsi Design, PD methodologies, coding constraints

Digital Logic Design, Verilog, System Verilog, analog IC design methods

closure , Perforce, routing, Git, Python, Tcl, Synthesis, cdc, Extraction, PPA targets, hierarchical hard-macro integration, MBIST, Scan, UPF, Floorplan, custom macros, Dft, timing power ECOs, RTL-to-GDS flow, partitioning, CPF, SRAMs, Clock Tree Synthesis

Voltus, Backend Signoff flows, Cell EM, LVS, SigEM, Power Grid planning, pegasus, Cadence Tools, Innovus, PERC, EMIR, Tempus, Esd, Signal and Power bump planning, DRC

Physical Design, Physical design strategies

Python, Tcl, Cadence Tools, EDA Tools, EM IR checks, Timing Closure, PDK management, low-power design, physical design methodology, foundry tapeout processes

Hard Macros (SerDes), Flip-Chip, PNR, Cadence Tools, Physical Implementation, FDSOI 22nm