Vcs, Spi, Pcie, System Verilog, ARINC-818, DO-254, QuestaSim, ADC interfaces, Axi, VHDL, ARINC-429, RFSOC FPGAs, Aldec

cache coherency , Noc, Pcie, Verilog, Clearcase, Python, Git, Perl, Tcl, architecture definition, RTL implementation, cdc, Infrastructure IPs, custom protocol design, RDC, memory systems, microarchitecture development, Synthesis, UALink, ESUN, AI scale-up interconnect fabrics, systemverilog, LINT, Timing Closure, performance optimization, CXL

Pcie, LINT, cdc, High-speed protocol, gasket bridge modules, RTL freeze, Dft, RDC, Timing Constraints, Multi Clock Reset Voltage and Power domain, SS LPDDR, Quality Check, SS Ethernet, SoC Chiplet design, SoC IP Design, micro-Architecture specification, SoC Integration, glue logic

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, UCIe, Uvm, systemverilog, AMBA, Axi

network infrastructure, C, Computer Networking, Pcie, Routing Protocols, I2c, Linux Kernel, L2 Switching, hash memories, SERDES, sonic, Networking OS, Enterprise Data Center, carrier network switching, NOS, DMA controllers, Marvell Switching Networking products, debugging skills, MDIO, TCAM, SAI

network infrastructure, C, Computer Networking, Pcie, Routing Protocols, I2c, Linux Kernel, L2 Switching, hash memories, SERDES, sonic, Networking OS, Enterprise Data Center, carrier network switching, NOS, DMA controllers, Marvell Switching Networking products, debugging skills, MDIO, TCAM, SAI

arm architecture , Uart, Pcie, Verilog, I2c, Flash, low power methodology, system debug infrastructure, RTL level checks, digital ASIC design, systemverilog, SSP, AMBA bus protocols, system memory hierarchy, constraints development, ARM based ecosystem components, multi-core SOC designs, DRAM, ARM v8 and v9 specifications, DC DC-T based synthesis