Perl, Tcl Scripting, Python, System Verilog, Synopsys Mentor VIPs, PCIe Gen3, random constraint-based testing, verification methodologies, performance power optimization, SMMU, CXL 1.1, Coresight architecture, assertion-based verification, Uvm, UPF, CHI protocols, Axi, formal verification, power-aware verification, coverage-driven testing, SVA

Clp, Pcie, Qc Tools, IPXACT, cdc, Vlsi, LINT, FIFO, UPF, AMBA, arbitration techniques, SDC, RDC, RTL Coding, VCLP

Spi, FPGA Design, Pcie, high speed board design, DDR-5, DDR-4, XFI, xaui, test and measurement equipment, XGMII

Pcie, Version Control, Ethernet, RTL synthesis, Documentation, Timing Closure, verification processes, silicon bring-up, bare metal firmware development, SERDES, AI tools like Cursor

Pcie, Ethernet, Python, characterization NRZ and PAM-4, Network Analyzers, Communication Protocols, high-speed SerDes validation, Oscilloscopes, BERTs, DCAs

Clp, Pcie, Qc Tools, IPXACT, cdc, Vlsi, LINT, FIFO, UPF, AMBA, arbitration techniques, SDC, RDC, RTL Coding, VCLP

clocking , Ovm, DDR, Pcie, Verilog, Ethernet, Platform bring up in Emulators or Silicon, SOC boot flow, Constrained-random verification environments, Uvm, systemverilog, Power management flows, C SV tests, Low Power Verification, Coverage report generation, System Verilog Assertions, RTL GLS level simulations

Pcie, LINT, cdc, High-speed protocol, gasket bridge modules, RTL freeze, Dft, RDC, Timing Constraints, Multi Clock Reset Voltage and Power domain, SS LPDDR, Quality Check, SS Ethernet, SoC Chiplet design, SoC IP Design, micro-Architecture specification, SoC Integration, glue logic

arm architecture , Uart, Verilog, I2c, Pcie, Flash, digital ASIC design, system memory hierarchy, AMBA bus protocols, constraints development, systemverilog, low power methodology, system debug infrastructure, multi-core SOC designs, DC DC-T based synthesis, RTL level checks, DRAM, ARM v8 and v9 specifications, SSP, ARM based ecosystem components

Clp, Pcie, Qc Tools, IPXACT, cdc, Vlsi, LINT, FIFO, UPF, AMBA, arbitration techniques, SDC, RDC, RTL Coding, VCLP