System Verilog, JTAG protocols, Logic Equivalency checking, ATPG, Post-silicon validation, Scan and BIST architectures

Vcs, System Verilog, primetime, Tessent, JTAG protocols, Logic Equivalency checking, ATPG, EDA Tools, TestMax, TetraMax, Scan and BIST architectures

boundary scan , Tcl, Perl, Vcs, Python, Test Architecture Methodology, EDA Tools, timing based simulations, Scan Insertion, Test static timing analysis, sdf debugging, Jtag protocols, Gate level simulation, Functional Verification, DFT CAD development, TestMax, p1687, p1500, ATPG, Infrastructure, BIST architectures, Timing Closure, Verilog design, DFT logic IP integration, Tessent tool sets, memory BIST, TetraMax

Vcs, Scan Insertion, ATE patterns, JTAG protocols, ATPG, Post-silicon validation, Tessent tool sets, P1687, TestMax, TetraMax, Gate level simulation debugging