Design for Manufacturability (DFM), Design for Yield (DFY), Shell, PERL, Tcl, Physical verification layout methodologies, Skill, DRC, LVS, Memory Layout, Semiconductor design flows

Python, Tcl, QRC, StarRC, Skill, ICC, Cadence Virtuoso, Calibre DRC LVS

Shell, PERL, Tcl, Assura, Skill, Memory layout design, Cadence Virtuoso

cadence schematic capture , Verification tools - CALIBRE, Cadence Tools, Memory layout design, AI automation in layout, ElectroMigration, Hercules, SKILL Programming, Physical verification LVS, ERC, DRC, Script Programming, Antenna, Chip Integration, Floor-planning, Hierarchy layout