Verilog, Rtl Design, RTL Coding, Micro-architecture, systemverilog, RTL Design Engineer

Unix, Linux, Perl, Tcl, Low power verification, floorplanning, Placement, power analysis, PNR implementation

Usb, DDR, Pcie, Verilog, Ethernet, LINT, cdc, Root Cause Analysis, AMBA protocols, Micro-Architecture Development, systemverilog, Synthesis, Axi, RDC, RTL Coding and Integration, Timing Analysis, APB, SERDES, Design Debug, ASIC SOC design, AHB, Rtl Design

Perl, Shell scripting, Python, Sta, SDC constraints, RTL design using Verilog, ASIC SoC development, Timing Analysis, systemverilog, digital design concepts, VHDL, Functional Verification, RTL debugging, UVM-based verification environments, Timing Closure, synthesis flows

cadence schematic capture , Hspice, high-speed custom digital design flows, AMs, Cadence Virtuoso, Spectre

power integrity , Perl, Python, Tcl, physical design sign-off, static dynamic IR drop, physical ECOs, Cadence Voltus, electromigration, power-grid optimization, PG strengthening, Ansys RedHawk, EM IR analysis, vectorless EM IR analysis

synchronicity , Unix, Perforce, Python, Shell Scripting, Git, Perl, Tcl, substrate noise analysis, Skill, Cadence custom IC Virtuoso platform, Cadence SKILL, starRC, Layout Automation, Calibre Physical Verification, ICV LVS, Analog Design environment, EMIR drop, agentic AI flows, finesim, Parasitic Extraction, PrimeSim, Virtuoso suite, SVRF

Pcie, Verilog, Ethernet, Synthesis, cdc, UALink, Simulation, timing considerations, UCIe, systemverilog, LINT, CXL