Systemc, Soc Architecture, Arm, Python, CHI, TLM 2.0, AMBA, RISC-V, scripting for modeling automation, CPU subsystems, Axi, memory hierarchies, BUS Protocols

rtl development , nand flash , Tcl, Verilog, FPGA Design, Python, Bash, Pcie, IP Integrator, Vivado Design Suite, VHDL, ChipScope ILA, Embedded Systems, Xilinx FPGAs

python, Signal Processing, Reliability Testing, weibull analysis, risk identification, random failure principles, ALt, Electronics, Measurement, statistical reliability analysis, reliability engineering, Bayes theorem, Test-to-Failure, FIT rate estimation methodologies, FMEDA, halt, ?²-statistics, reliability prediction, reliability calculations, Sensors, accelerated stress testing, FTA, environmental validation, HAST

control logic , Verilog, Rtl Design, Synthesis, systemverilog, Error handling, cdc, Sta, Ethernet standards, Digital micro-architecture, PCS functionality, Link monitoring, state machines, Packet processing, RDC, Safety mechanisms

Vcs, Perl scripting, Verilog, Python, Tcl, LINT, cdc, high-speed interfaces, ARM-based SoC architecture, Xcelium, AMBA protocols, systemverilog, RDC, Synopsys Design Compiler, Questa

logic bist , static timing analysis, UNIX, Jtag, Linux, Perl, Verilog, Tcl, DFT techniques, Synthesis, Scan Insertion, memory BIST, waveform debugging tools, equivalency checking, ATPG, EDA Tools, scan compression architecture, SSN Scan, IEEE standards, c-shell

Fpga, C, Soc Architecture, Verilog, Scripting Languages, digital logic design principles, systemverilog, logic synthesis techniques, RTL design concepts, ASIC design methodologies, low-power design techniques, emulation platforms, assertion-based formal verification