C, Routing, Perl, Tcl, Clock Planning, primetime, floorplanning, ICC2, LEC, Calibre, Innovus, Physical Verification, Placement, Timing Closure, Physical Design Implementation, EDA Tools

Scripting, Python, Routing, Tcl, CTS, primetime, 3D IC, Cadence, LVS, IR Drop, Innovus, Calibre, Physical Verification, HBM, Placement, Si, Chiplets, floorplanning, EM, Full-Chip Physical Design, Advanced Packaging, Timing Closure, DRC, EDA Tools, 2.5D, Advanced nodes 7nm or below, Synopsys ICC2

power supplies , C, I2c, Python, Labview, Automation of Equipment and Tests, SVI3, scopes, Relays, ATE programs, PMBUS, Computer to IC board communications, Basic circuits on bread board, SVID, Probes, SPMI, Power Chip Communication protocols, Validation related equipment, Load Slammer, FPGAs, Multi-meters, Bench Validation, Debug of Power Management ICs, Design PCBs, Analog switches

UPF, script writing in Python, UVM Test Bench development, power simulation on VCS

synopsys tools , Perl, Tcl, SoC integration, high-speed designs, ICC2, Process Improvements, Physical Verification, flow automation, Floor Planning, Calibre, Innovus, Netlist2GDSII implementation, power grid design, Tk

Debugging, Linux Scripting, Python, triaging, AI GenAI systems, Vlsi, EDA Tools, orchestration systems, agent frameworks

clock distribution , Clp, PERL, Tcl, low power design, Sta, PERC, LVS, LEC flow, Tape Out, IP integration, Dfm, Timing Closure, Physical Verification, Synthesis, Gds, Tk, cpf, Clock Tree Synthesis, upf, PNR, Physical Design, ERC, DRC, Floorplan, Power and Signal Integrity Analysis

Tcl Scripting, Formality LEC, Low Power Formal LEC ECO, Conformal ECO, Cadence, Synopsys, VC-LP

Unit Testing, Tcp, C++, Data Structures, Http, Python