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Showing 9 jobs
Skills:
Unix, Linux, Perl, Tcl, Low power verification, floorplanning, Placement, power analysis, PNR implementation
Skills:
Perl, Python, Tcl, Timing Closure STA, RTL-to-GDSII Execution, Red Hawk, Programming Scripting, Fusion Compiler, LEC, Tempus, Cross-Functional Collaboration, Physical Formal Verification, Innovus, Calibre, primetime, PPA Optimization, EDA Tools, VCLP
Skills:
Computer Engineering, Tcl, low-power designs, Computer Science, Electrical Engineering, coding constraints
Skills:
Routing, Perl, Python, Tcl, CTS Clock Optimization, floorplanning, Placement Optimization, IR EM, Synopsys Fusion Compiler, Cadence Innovus, Physical Signoff, Power Planning, Eco, MMMC, PPA Optimization, STA Timing Closure, VLSI Physical Design, Synopsys ICC2
Skills:
redhawk , Verilog, Shell, PERL, Tcl, Fusion Compiler, Innovus, Calibre, VHDL, Starrcxt, place and route methodologies, low power physical design flows and methodologies, physical implementation and analysis tools, timing and signal integrity analysis, power integrity and reliability analysis, power grid planning and implementation, timing and metal-only ECOs, post-route timing optimization, placement and optimization, floorplan exploration and optimization, Clock Tree Synthesis
Skills:
Perl, Python, Tcl, Sta, CTS, pegasus, floorplanning, Cadence Toolchain, Power Grid, Tempus STA, Innovus, Calibre, MMMC, Timing Closure, Sign-off, ECO generation, SI crosstalk analysis, GDSII
Skills:
static timing analysis, Perl, Tcl, Makefile scripting, Synthesis, physical design CAD flow, Mentor Calibre, Power Distribution, Cadence Innovus, Cadence Genus, Floor Planning, physical design verification
Skills:
redhawk , Python, Routing, Apache, Perl, Tcl, physical design methodologies, floor-planning, CTS, LVS, PPA tradeoffs, Calibre, Physical Verification, Extraction, StarRC, Synopsys fusion compiler, floor plan synthesis, Synthesis, CPU physical design, EM, Ir, signoff, Place And Route, Timing Closure, DRC, Placement, Cadence PrimeTime
Skills:
Synthesis, physical verification closure, Formal, Timing Closure, block chip level implementation from Netlist to GDS, scripting skills – TCL
