Usb, Pcie, Perl, Shell scripting, Python, Tcl, Cadence, Mentor, IEEE 1149.1 JTAG, IEEE 1500, DFT architecture, Analog Mixed-Signal test structures, ATPG, EDA Tools, IEEE 1687 IJTAG, Siemens, Synopsys

Shell, Jtag, Python, Tcl, IEEE 1149.x, scan compression, DFT methodologies, MBIST, DFT EDA tools, IEEE 1687, ATPG, LBIST

Perl, Shell scripting, Python, Tcl, Scan Insertion, ATPG, Scan Compression, MBIST, Siemens Tessent

Perl Shell Scripting, Stuck at Transition ATPG, Production enablement, Scan Insertion, Synopsys Tetramax DFTMAX, DFT Silicon bring up expertise, Silicon Debug for Phasing closure, Yield Analysis Debug, Test cost reduction analysis, Scan Architecture, VCS simulation tool, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features

C, Vcs, Jtag, Perl, Verilog, Python, Tcl, Verdi, MBIST, DFT micro-architecture, Synopsys Tetramax, EDA Tools, Scan, Mentor Tessent

coverage analysis, Scan Insertion, SoC level DFT Activities, ATPG, Timing simulations, Pattern generation, Unit delay

Jtag, Perl, Verilog, Python, Tcl, gate-level DFT simulations, Scan Insertion, Cadence DFT EDA tools, MBIST, Siemens Tessent, Synopsys TestMAX, systemverilog, DFT implementation and verification, DFT rule checking, ATPG, scan chain stitching, Boundary Scan BSCAN

boundary scan , Verilog, Python, Cadence Tools, ATPG, MBIST, Synopsys

boundary scan , Vcs, Perl, Python, System Verilog, Tcl, Memory BIST, primetime, Logic Equivalency checking, TetraMax, Scan and BIST architectures, Gate level simulation debugging, JTAG protocols, ATPG, EDA Tools, Tessent tool sets, TestMax