Jtag, Perl, Tcl, Memory BIST, Fusion Compiler, ATPG, AI-assisted workflows, Genus, Scan insertion techniques, Primetime STA, Scan architecture

layout verification , System Verilog, Computer Engineering, Tcl, ASIC Design, Electrical Engineering, Computer Science, design rules, low power designs

Logic Design, On-chip scan compression, Scan BIST, Fault Simulation, ATPG

python, perl, Data Analysis, silicon design, Debug, System Validation, Hardware Design

bist , Perl, Debugging, Python, Tcl, Logic Design, Sta, RTL, Scan, make, tessent, on-chip scan compression, gate level simulation, Fault Models, automation methods, ATPG, pattern generation, VLSI simulation tools, Fault Simulation