static timing analysis, EDA tools for synthesis, VHDL, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, low-power design techniques, digital IC ASIC design, RTL quality tools such as Spyglass Lint CDC RDC

Timing Analysis, RTL Coding, Digital circuit design principles, Logic Synthesis, Simulation and verification methodologies, Debugging and troubleshooting complex digital systems, Power optimization techniques

Static timing analysis, Soc, Verilog, quality assurance, AHB, Timing Constraints, LINT, systemverilog, Design Verification, cdc, Logic Synthesis, ASIC, physical implementation, AXI Stream, low power design, formal equivalence, APB, Dft, power analysis