static timing analysis, Verilog, Python, Tcl, SDC development, Tempus, Cadence Innovus, simulation methodologies, Rtl Design, transistor-level concepts, Genus, digital circuit operation, custom layout fundamentals, place-and-route, multi-clock designs, Synthesis, digital design fundamentals, floorplanning, Physical Verification, systemverilog, CDC concepts, Timing Constraints, Liberty timing models, characterization concepts

rtl development , Vcs, Gdb, Shell, Perl, Verilog, Python, ASIC design flow, floor-planning, scripting knowledge, Simulation Tools, Timing Analysis, Logic Synthesis, debug tools, Eco, design and verification tools, micro-architecture, Debussy, bring-up lab debug

bandgap references , power converters , Design extraction and simulation flows, Analog layouts, Source-Sink LDOs, Voltage Regulators, High speed level shifters, Current Sense SAR ADCs, FET layouts, Analog Circuit Design, Power Management ICs, Temperature Sensor, Switch Cap circuits, Ultra-low power Oscillators, Comparators, Design flows and methodologies, Noise isolation techniques, Op-Amps, Analog Buffers, Charge Pumps

Verilog, Tcl, Ethernet, Perl, C, Scripting Languages, Pcie, AHB, Flash interfaces, RDC constructs, IP Synthesis, IP development flow, QuadSPI, FPGA Emulation Board, Axi, SERDES, BUS Protocols, HDLs, DDR4, High Speed Serial protocols, ATPG, cdc, AMBA, Testplan development, VHDL, microcontroller architecture, pre silicon validation, LPDDR4, Dft

redhawk , Verilog, Fusion Compiler, Metal-only ECO Implementation, Timing Optimization, Signal Integrity Analysis, FLASH Process Technologies, Floorplan Exploration, Innovus, Calibre, low power design, GDSII Flow, VHDL, Physical Design, Starrcxt, Reliability Analysis, Clock Tree Synthesis

redhawk , Tcl, Verilog, PERL, Timing Optimization, Signal Integrity Analysis, Starrcxt, FLASH Process Technologies, Fusion Compiler, Calibre, Innovus, Power Grid Planning, VHDL, Physical Design, Clock Tree Synthesis, Reliability Analysis, Timing Closure

Verilog, Pcie, Low power estimation, Low power RTL design, Microarchitecture synthesis, LINT, Timing Closure, Rtl Design, CXL, cdc