Static checks (Lint, rtl development , Power checks), Clock power domain implementations, Verilog Hdl, Synthesis timing analysis, Power management and low-power design techniques, digital hardware design, ARM System Architectures, DFT and physical implementation flows, Micro-architecture specifications, ARM-based designs, cdc, RDC, Advanced synthesis checks

rtl development , Vcs, Gdb, Verilog, ASIC design flow, floor-planning, Timing Analysis, Logic Synthesis, Eco, design and verification tools, micro-architecture, Debussy, bring-up lab debug

redhawk , Verilog, Shell, PERL, Tcl, Fusion Compiler, Innovus, Calibre, VHDL, Starrcxt, place and route methodologies, low power physical design flows and methodologies, physical implementation and analysis tools, timing and signal integrity analysis, power integrity and reliability analysis, power grid planning and implementation, timing and metal-only ECOs, post-route timing optimization, placement and optimization, floorplan exploration and optimization, Clock Tree Synthesis

code coverage , Oops, Usb, Networking, Cpu, DDR, Pcie, Verilog, Ethernet, Arm, LINT, cdc, SV, SV METH, C tests, Axi, AMBA, spyglass, VHDL, SoC Verification, Graphics, RTL Coding, AHB

rtl development , static timing analysis, Verilog, Digital Signal Processing, LINT, Synthesis, Debug, LEC, Simulation, Matlab modeling, FPGA prototyping

Unreachability (UNR) analysis, RTL and Gate-Level Simulations (GLS), Formal Property Verification (FPV), Reset Domain Crossing (RDC) assertions, SystemVerilog (SV), Shell scripting, UVM methodologies, Connectivity checks, Power-aware simulations

Python, Tcl, floorplanning, Physical design flows, Logical Equivalence, Clock CTS, Synthesis, Timing Analysis, EDA Tools, Budgeting, Physical Verification DRC LVS ERC, Place And Route

power integrity , Routing, Perl, Python, Tcl, Physical Sign off, Chip finishing, Metal fill, Tapeout checks, Clock Trees, Physical Verification, Sealring, Signal Integrity, RTL2GDS flow, Floorplans, Power Distribution Network, Physical Design, Placement, Timing Closure, Equivalence Check, Synthesis Constraints

Spi, I2c, Uart, Pcie, Usb, Noc, cdc, SoC IP Design, AMBA protocols, Network on Chip