Senior Analog Circuit Design Engineer

Experience-(4–8 Years)

Location: Bengaluru

About the Role

Join a high-performance silicon engineering team designing next-generation analog and mixed-signal IP for advanced SoCs. You will own the design, simulation, verification, and silicon validation of critical analog circuits, collaborating closely with architecture, layout, and product engineering teams to deliver first-pass silicon success.

Key Responsibilities

Design and optimize analog building blocks including LDOs, Bandgap References, PLL/DLL circuits, Bias Generators, Comparators, Op-Amps, Current Mirrors, Oscillators, Level Shifters, and Clock Buffers.
Perform transistor-level design, schematic capture, simulation, and post-layout verification across PVT, Monte Carlo, mismatch, noise, and reliability conditions.
Partner with Analog Layout engineers to optimize matching, parasitics, EM/IR, and manufacturability.
Support silicon bring-up, characterization, and root-cause analysis of post-silicon issues.
Drive design reviews and contribute to IP quality, performance, power, and area optimization.

Required Qualifications

B.E./B.Tech/M.E./M.Tech in Electronics or related discipline.
4–8 years of hands-on experience in analog or mixed-signal IC design.
Strong expertise in CMOS Analog Circuit Design and transistor-level analysis.
Experience with Cadence Virtuoso, Spectre, ADE XL/Assembler, and extraction tools such as Calibre xRC/StarRC.
Good understanding of analog layout techniques, device matching, noise, stability, compensation, and reliability.
Scripting knowledge in Python, SKILL, Perl, or TCL is a plus.

Preferred Experience

Experience designing analog IP for CPU, GPU, AI Accelerator, Networking, or High-Performance SoCs.
Exposure to advanced technology nodes (FinFET) and low-power design methodologies.

What You'll Bring

Strong analytical and debugging skills.
Ownership mindset with a passion for solving complex analog design challenges.
Ability to collaborate effectively in a fast-paced, cross-functional engineering environment.