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Showing 4 jobs
Skills:
Vcs, Scan Insertion, ATE patterns, JTAG protocols, Tessent, Gate level simulation, ATPG, Post-silicon validation, P1687, TestMax, TetraMax
Skills:
Vcs, ATE patterns, Scan Insertion, JTAG protocols, ATPG, Gate level simulation, Post-silicon validation, Tessent tool sets, P1687, TestMax, TetraMax
Skills:
Vcs, Scan Insertion, ATE patterns, JTAG protocols, ATPG, Post-silicon validation, Tessent tool sets, P1687, TestMax, TetraMax, Gate level simulation debugging
Skills:
Verilog, IEEE 1500, VHDL, ASIC Development, IEEE 1149.1, EDA tools for ASIC design verification and testing, Low-power design techniques
