Similar Jobs - 61045726

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ASIC DFT Engineering Technical Leader | ATPG, MBIST, SSN, SCAN | 12+ years

12-14 yrs

Chennai, India

Skills:

Vcs, System Verilog, ATE patterns, JTAG protocols, Logic Equivalency checking, ATPG, Post-silicon validation, Scan and BIST architectures, Gate level simulation debugging

Early Applicant

ASIC DFT Engineering Technical Leader | ATPG, MBIST, SSN, SCAN | 12+ years

Cisco Home

12-14 yrs

Chennai, India

Skills:

Vcs, Static Timing Analysis, System Verilog, Post-silicon validation, DFT CAD development, Logic Equivalency checking, JTAG protocols, ATPG, Test Architecture Methodology, P1687, Scan and BIST architectures, Gate level simulation debugging, ATE patterns, Verilog design

Early Applicant