C, Gdb, Verilog, Python, Scripting Languages, Synthesis, SOC development, Rtl Design, Cadence, RTL Build, Design Automation, Timing Closure, Verification, ASIC architecture, Physical Design, Dft, Micro-Architecture, Indago

Usb, Pcie, Perl, Verilog, Python, Makefiles, RTL Build flows, AMBA protocols, Debug architecture, Axi, SoC Clocks, SDCC, APB, RST, SOC design, AHB, System-Verilog

arm architecture , Uart, Pcie, Verilog, I2c, Flash, low power methodology, system debug infrastructure, RTL level checks, digital ASIC design, systemverilog, SSP, AMBA bus protocols, system memory hierarchy, constraints development, ARM based ecosystem components, multi-core SOC designs, DRAM, ARM v8 and v9 specifications, DC DC-T based synthesis

System Verilog, Logic Design, design closure techniques, digital design fundamentals, SoC integration, RTL Coding, synthesizable Verilog, timing power convergence tools, Simulation Tools

Verilog, Microprocessors, Usb, Logic Design, Pcie, LINT, cdc, pad ring, SoC clocking, Design Compiler, Asynchronous interface, Synthesis, SDCC, RTL Coding, micro-architecture, Low power SoC design, System-Verilog, constraint development, SOC design, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, APB, timing concepts for ASIC, Timing Closure, Multi Clock designs, AHB

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency