Perl, Verilog, Python, Makefiles, RTL Build flows, SoC Clocks, System-Verilog, Synthesis, RST Debug architecture

arm architecture , Uart, Verilog, I2c, Pcie, Flash, digital ASIC design, system memory hierarchy, AMBA bus protocols, constraints development, systemverilog, low power methodology, system debug infrastructure, multi-core SOC designs, DC DC-T based synthesis, RTL level checks, DRAM, ARM v8 and v9 specifications, SSP, ARM based ecosystem components

UFS (Universal Flash Storage), C, C++, Vcs, Makefile, Perl, Verilog, Ethernet, System Verilog, System Verilog verification language, Uvm, System Verilog assertion and coverage code, Synopsys VIPs, Waveform analyzer, Asic Design Verification, ASIC flow, Processor based SoC level verification, AXI-AMBA protocol variants, PCIe Protocol

quality assurance practices, microarchitecture RTL design coding, clock domain crossing analysis and implementation techniques, secure development in logic design, timing power convergence methodologies and tools, systemverilog

Perl, Python, Tcl, Functional Coverage, Uvm, SVA, systemverilog, ASIC SoC Subsystem IP verification