redhawk , Routing, Perl, Python, Tcl, SDC constraints, Design Compiler, CTS, primetime, Fusion Compiler, RTL-to-GDS implementation, Voltus, ECO implementation, Full Chip Physical Design, Synthesis, MCMM timing closure, Physical Design methodologies, EM IR analysis, Synopsys ICC2

redhawk , Tcl, Perl, Python, SDC, Foundry PDKs, Implementation tool suite, EDA Tools, Power gating, Cadence, primetime, Tempus, Synopsys ICC2, CPF, Timing Analysis, TSMC, Physical Design, Synopsys, UPF, Cadence Innovus, Sta, Multi-voltage domains, Voltus, Signoff tools, Samsung, Low-power design techniques

Debugging, Perl scripting, Cadence Tools, IP QA, Mentor Calibre, CMOS circuit design fundamentals, Innovus, RTL2GDS, CMOS layouts, Apache RedHawk, Genus, Synopsys Prime Time

Python, Routing, Perl, Tcl, primetime, ICC2, Back End Physical Design, LVS, Physical Verification, Extraction, STA timing closure, StarRC, Placement, Synopsys Design Compiler, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, Floorplan Physical Implementation, ICC Fusion Compiler, CTS Timing Closure, DRC, PNR tools

PERL, Python, Tcl, Sta, CTS, Timing Convergence, RTL2GDSII flow, ICC2, Ir, Tempus, Block-level and Full-chip Floor-planning, primetime, Innovus, Physical Verification, Synthesis, Layout Closure, Physical Design, High Frequency Design Methodologies, Seahawk, Place And Route, ECO Timing Closure

Scripting, Floor-Planning, AI tools, Cadence, RTL2GDS flow, Chip Finishing, flow automation, Physical Verification, Synthesis, Physical Design, Power Distribution, Metal Dummy Fill, Synopsys, Place And Route, Clock Tree Synthesis

Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology

EM IR understanding and fixes, PV closure, Util area reduction experiments, Physical aware Synthesis using FC, ECO cycle, STA analysis, PnR-Floorplan Macro placement, Density Congestion Timing issues and fixes on lower tech nodes 5nm

Routing, Physical Design Methodologies, Tcl tool scripting, RTL-to-GDSII implementation, DDR design knowledge, primetime, Placement, Calibre, Genus, Innovus, floorplanning, MultiTap-CTS