arm architecture , Uart, Pcie, Verilog, I2c, Flash, low power methodology, system debug infrastructure, RTL level checks, digital ASIC design, systemverilog, SSP, AMBA bus protocols, system memory hierarchy, constraints development, ARM based ecosystem components, multi-core SOC designs, DRAM, ARM v8 and v9 specifications, DC DC-T based synthesis

Perl, Verilog, Python, Makefiles, fuse floorsweep design, RTL Build flows, SOC Assembly, Design Automation, Rtl Design, padring, System-On-Chip design implementation flow, SOC integration

Perl, Verilog, Python, Makefiles, RTL Build flows, SOC Assembly, pinmuxing, SoC Verification, Design Automation, chip level front-end design, Physical Design, Rtl Design, Dft, Synthesis, padring, retiming, System-On-Chip design implementation flow, SOC integration

Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation

Usb, Vcs, DDR, Pcie, Perl, Ethernet, Shell scripting, Python, Tcl, Xcelium, Uvm, systemverilog, Questa

Computer Architecture, reset methodologies, Timing Constraints, Microarchitecture, digital RTL design