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Job Description:

We are looking for a skilled and motivated DFT Engineer with 5+ years of experience in VLSI design. The candidate will be responsible for handling DFT activities (Boundary scan, Memory BIST andscan insertion, ATPG, gate-level simulations and Silicon Bring up and failure debug on ATE) across complex SoC/IP designs and will work closely with RTL and STA teams to ensure high-performance and power-efficient silicon implementation.

Key Responsibilities:

Perform block-level and full-chip DFT activities for ASIC/SoC designs.
Boundary scan insertion, Memory BIST insertions and Scan insertions with compression logic
Understanding and fixing the DFT DRCs rules
ATPG (stuck-at , transition and Iddq mode)
Patterns verification with timing and debug DFT issues across RTL/Gate-level stages
Collaborate with ATE teat to support first silicon bring-up , failure analysis

Required Qualifications:

Bachelor's or master's degree in Electronics, Electrical Engineering, VLSI, or related field.
5+ years of hands-on experience in Design For Testability for ASIC/SoC designs.
Strong understanding of digital design fundamentals and timing concepts.
Experience with industry-standard DFT tools such as Siemens, Cadence and Synopsys
Good knowledge on DFT DCR rules
Familiarity with scripting languages such as Tcl, Perl, or Python.
Strong analytical, communication, and teamwork skills.

Requirements/Qualifications:

Bachelors Degree in Electronics Engineering.

Senior Engineer I Design