Vcs, System Verilog, ATE patterns, JTAG protocols, Logic Equivalency checking, ATPG, Post-silicon validation, Scan and BIST architectures, Gate level simulation debugging

Vcs, System Verilog, primetime, TestMax, Logic Equivalency checking, EDA Tools, JTAG protocols, ATPG, Scan and BIST architectures, TetraMax, Tessent