boundary scan , Vcs, Static Timing Analysis, System Verilog, DFT CAD development, Memory BIST, Logic Equivalency checking, Post-silicon validation, P1687, Gate level simulation debugging, Scan and BIST architectures, Verilog design, ATE patterns, JTAG protocols, ATPG, Test Architecture Methodology

boundary scan , Vcs, Static Timing Analysis, System Verilog, DFT CAD development, Memory BIST, Logic Equivalency checking, Post-silicon validation, P1687, Gate level simulation debugging, Scan and BIST architectures, Verilog design, ATE patterns, JTAG protocols, ATPG, Test Architecture Methodology

boundary scan , Vcs, Perl, Python, System Verilog, Tcl, Memory BIST, primetime, Logic Equivalency checking, TetraMax, Gate level simulation debugging, Scan and BIST architectures, JTAG protocols, Scripting skills, ATPG, EDA Tools, Tessent tool sets, TestMax