Perl, Python, Tcl, Sta, CTS, pegasus, floorplanning, Cadence Toolchain, Power Grid, Tempus STA, Innovus, Calibre, MMMC, Timing Closure, Sign-off, ECO generation, SI crosstalk analysis, GDSII

redhawk , Python, Routing, Apache, Perl, Tcl, physical design methodologies, floor-planning, CTS, LVS, PPA tradeoffs, Calibre, Physical Verification, Extraction, StarRC, Synopsys fusion compiler, floor plan synthesis, Synthesis, CPU physical design, EM, Ir, signoff, Place And Route, Timing Closure, DRC, Placement, Cadence PrimeTime

Routing, Sta, CTS, floorplanning, EM, Ir, LVS, Physical Implementation, Synthesis, Physical Design, Placement, Si, DRC, RTL Netlist, Timing Closure, Tape-out, Power Domains, GDSII, Hierarchical Designs

Unix, Linux, Perl, Tcl, Low power verification, floorplanning, Placement, power analysis, PNR implementation

Routing, Perl, Python, Tcl, CTS Clock Optimization, floorplanning, Placement Optimization, IR EM, Synopsys Fusion Compiler, Cadence Innovus, Physical Signoff, Power Planning, Eco, MMMC, PPA Optimization, STA Timing Closure, VLSI Physical Design, Synopsys ICC2

Scripting, Static Timing Analysis, Routing, Design Compiler, CTS, primetime, ICC2, Synopsys Fusion Compiler, LVS, Cadence Genus, Innovus, Physical Verification, Formal Equivalence, Extraction, StarRC, Placement, RTL to GDS2 flow, Floor-plan Physical Implementation, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, Physical Design, Timing Closure, DRC, PNR tools

EM IR understanding and fixes, PnR-Floorplan Macro placement, STA analysis, Util area reduction experiments, ECO cycle, Physical aware Synthesis using FC, PV closure, Density Congestion Timing issues and fixes