power integrity , Pvs, Static Timing Analysis, Python, Tcl, primetime, ICC2, Cadence Innovus, Synopsys Fusion Compiler, LVS, Dfm, Calibre, Physical Verification, StarRC, UCIe PHY Integration, Antenna, floorplanning, EM, IR-drop, Place-and-Route, Thermal-aware Placement, Physical Design, ERC, Timing Closure, DRC

routing, floorplanning, physical optimization, LVS, physical ECO implementation, Cadence Innovus, congestion analysis, Physical Verification, sign-off, Placement, IR drop, Calibre, antenna checks, Physical Design, primetime, Synopsys ICC2, Timing Closure, ERC, DRC, Power Planning, RTL-to-GDSII, StarRC

power integrity , Chip-Package Co-Design, Physical Design, floorplanning, Bump Planning, Package Interface Design, Signal Integrity, EDA Tools, Package Design

synopsys primetime , Routing, Perl, Python, Tcl, CTS, PTPX, Cadence Tempus, SDC, Synthesis, Eco, MMMC, Physical Design, STA Timing Closure, Digital Design

Synopsys - ICC, Shell scripting, Tcl, Routing, Perl, Power grid analysis, Timing Closure, Place and Route tools, Antenna fixing, Floorplan, DRC-LVS closure, Signal Integrity, Placement, Physical Design, Cadence – Innovus Encounter

Tcl, C, Perl, Physical Verification, Timing Closure, floorplanning, Physical Design Implementation, Clock Planning, Placement and Routing

EM IR understanding and fixes, PV closure, Util area reduction experiments, Physical aware Synthesis using FC, ECO cycle, STA analysis, PnR-Floorplan Macro placement, Density Congestion Timing issues and fixes on lower tech nodes 5nm

Flows, Physical Design, verbal and presentation skills, Design Methodologies, debugging skills, sign-off tools