C, Perl, Verilog, Python, Tcl, VHDL, Uvm, systemverilog

Usb, Perl, Verilog, Sata, Python, DV methodologies, PCI Express, Uvm, systemverilog, VMM, constrained random verification, functional coverage

C, Software Development Life Cycle, Data Analytics, Python, Protocol analyzers, IO tools, Debugging tools for Embedded Systems, Embedded system concepts and architecture, Github Copilot, Ai, ML models

Fpga, Vcs, Pcie, Ethernet, Xcelium, Emulation, Uvm, systemverilog, Dft, Questa, DDR5, DDR4

C Programming, SOC Chip level Cluster Sub-System Verification, Protocols like AHB AMBA AXI ACE OCP, Multimedia Networking protocols like PCIe gen3 MIPI CSI2 GPU Automotive Ethernet TSN USB DSP Image RADAR processing, Automotive protocols like LIN CAN, System Verilog UVM, Microcontroller and Microprocessor architecture, Memory Flash SRAM LPDDR DDR3 4 SD eMMC and memory controllers, ARM Cores, Verification using formal methods, Interconnect NIC FlexNoC Cache Coherency

Ovm, Perl scripting, Verilog, Post-silicon bring-up HW-SW debug, AXI protocol, DDR PHY architecture, Uvm, JEDEC standards, systemverilog, DFI protocol, LPDDR4, debug and root-cause skills, SS SoC post-silicon issues, AHB, LPDDR5