Verilog, Oops Concepts, scripting and tool development using Perl, VCS or equivalent simulation tools, debug tools like Debussy GDB, VMM, Uvm, systemverilog

Noc, C, Pcie, Perl, Python, Reset and power verification, SOC verification methodologies, SOC bring-up, Uvm, Post-silicon verification, Axi, HW FW interaction verification, Coherency verification, Bus Fabric, AHB, UPF integration

simvision , Cadence Tools, SV UVM-based mixed-signal testbench development, Xcelium, VIVA, Behavioral modeling using SV-RNM Verilog-AMS, SoC-AMS testbench development, Virtuoso ADE, Assembler

Computer Architecture, Perl, Debugging, Python, Formal Verification methodologies, IP SOC verification, Functional Verification, Uvm, systemverilog, Rtl Design

Shell, Python, Perl, Scripting Languages, DACs, Uvm, SV, Dms, behavioral modeling, Signal Processing, digital RTL, ADC, Synopsys VCS, Analog Mixed Signal, DV, full chip verification, Cadence Virtuoso, verification plan, Oscillators, Pll, Debug

wireless protocols , modem, System Verilog, Wifi Standards, constraint random tests, assertion coverage-based verification methodology, debugging RTL TB issues using Verdi, Uvm, formal static verification methodologies