Jasper, Perl, Python, Asic verification, verification methodologies, Synopsys Magellan, Uvm, systemverilog, Cadence IEV, VC Formal, functional coverage, SVA

Debugging, System Verilog, Axi, Problem-solving skills, CHI, ARM bus protocols, APB, SoC system architecture, Uvm, AHB, Virtual Memory concepts

Jtag, Perl, Verilog, System Verilog, Python, Tcl, Mentor Questa, Cadence Xcelium, JasperGold, Uvm, multi-clock domain mixed signal designs, Root Cause Analysis, debugging of complex mixed signal designs, Synopsys VCS, APB, constraint-random test generation, CRI, IJTAG

static timing analysis, Digital Logic Design, Perl, Verilog, Python, Scripting, Tcl, Synthesis, memory subsystems, cdc, SOC design, Uvm, IP integration, systemverilog, Rtl Design, Axi, formal verification, EDA tool flows, LINT, Verification, bus architectures, automation of design flows

Shell, Perl, Verilog, Python, Tcl, UVM methodology, Cadence, systemverilog, Functional and code coverage, Simulation and debugging concepts, Verification tools from Synopsys, Siemens EDA

Tcp, Pcie, Ethernet, System Verilog, RDMA, Data path verification performance tests, Building test benches from scratch, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

Usb, Ovm, Soc, DDR, Pcie, Ethernet, System Verilog, Ip, Uvm, Video, MIPI, VMM, ARM Based SoC Verification, HDMI, dsi, CSI

Video Codecs, Python, Perl, Shell, AHB, Uvm, ZeBu, systemverilog, Palladium, Axi

Usb, Fpga, Soc Architecture, Pcie, Perl, Debugging, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, AMBA, formal verification, Test Bench, transaction level modeling, AXI4