Perl, Python, Tcl, Sta, CTS, pegasus, floorplanning, Cadence Toolchain, Power Grid, Tempus STA, Innovus, Calibre, MMMC, Timing Closure, Sign-off, ECO generation, SI crosstalk analysis, GDSII

Shell, Perl, Python, Tcl, Ecos, Flows, automation, Innovus, primetime, ICC2, Tempus, FusionCompiler, Design Reviews, EM closure, Ir, PD methodologies, tapeout readiness, RTL-to-GDSII flow, Timing Closure, Si, PPA optimization

Computer Engineering, Tcl, low-power designs, Computer Science, Electrical Engineering, coding constraints

Routing, Perl, Python, Tcl, CTS Clock Optimization, floorplanning, Placement Optimization, IR EM, Synopsys Fusion Compiler, Cadence Innovus, Physical Signoff, Power Planning, Eco, MMMC, PPA Optimization, STA Timing Closure, VLSI Physical Design, Synopsys ICC2

Scripting, Static Timing Analysis, Routing, Design Compiler, CTS, primetime, ICC2, Synopsys Fusion Compiler, LVS, Cadence Genus, Innovus, Physical Verification, Formal Equivalence, Extraction, StarRC, Placement, RTL to GDS2 flow, Floor-plan Physical Implementation, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, Physical Design, Timing Closure, DRC, PNR tools

Synthesis, physical verification closure, Formal, Timing Closure, block chip level implementation from Netlist to GDS, scripting skills – TCL

Tcl, PERL, Tk, Cadence Innovus