routing, congestion analysis, IR drop, primetime, floorplanning, physical ECO implementation, physical optimization, Cadence Innovus, LVS, Power Planning, Physical Verification, antenna checks, Calibre, Physical Design, StarRC, ERC, Timing Closure, DRC, Placement, sign-off, RTL-to-GDSII, Synopsys ICC2

Perl, Python, Tcl, low-power physical design implementation, STA electrical checks, top-level floorplanning, ASIC Design, Physical Verification, block integration

Tcl Scripting, Formality LEC, Low Power Formal LEC ECO, Conformal ECO, Cadence, Synopsys, VC-LP

Perl, Python, Tcl, OCV, primetime, Fusion Compiler, ICC2, SI Crosstalk, ECO flows, MMMC, Timing Closure, POCV, AOCV, Clock Tree Synthesis

Tcl Scripting, ECO Implementation, Formality LEC, Conformal ECO, Cadence, CPF, Synopsys, UPF, VC-LP

Tcl, PERL, Cadence Innovus, Tk

redhawk , Tcl, Python, Perl, Scripting Languages, Tempus, manufacturing sign-off, multi-clock domain handling, advanced nodes, ASIC SoC physical design, PrimeClouser, Cadence Innovus, Timing Analysis, Physical Verification, EDA Tools, DFT insertion, Calibre, EM IR analysis, primetime, Signal Integrity, low-power design, Voltus, reliability checks, power analysis