Python, scoreboarding, Mentor Questa, Cadence Xcelium, AXI protocol, SystemVerilog UVM, GLS, Synopsys VCS, memory controller architecture, assertions SVA, DDR protocol JEDEC specifications, functional coverage

Ethernet, Pcie, Mentor, Synopsys, Uvm, systemverilog, Verification of IP AMS systems, Protocol VIP integration, Cadence, PAM4, Register modeling, D2D, Avery, PAM2, Advanced verification methodologies

Ethernet, Pcie, Synopsys, Uvm, advanced verification methodologies, systemverilog, Mentor, Cadence, PAM4, Register modeling, D2D, protocol VIP integration, Avery, PAM2

cache coherency , Vcs, Perl, Python, Tcl, CHI, Ace, Xcelium, GPU Verification, AMBA protocols, NoC Integration, coverage-driven verification, SystemVerilog UVM, constrained-random verification, Performance Validation, Axi, Questa, SVA assertions

Ovm, Verilog, Python, Functional Verification, Asic verification, formal verification, systemverilog, Uvm

Tcl, Verilog, Python, Perl, Uvm, SVA, VHDL, systemverilog