Perl, Python, Tcl, Ansys RedHawk, Static and dynamic IR analysis, Power integrity analysis, Cadence Voltus, Power grid optimization

logic bist , Usb, Perl, Pcie, Shell scripting, Static Timing Analysis, Python, Tcl, Memory BIST, Mentor, Cadence, IEEE 1149.1 JTAG, IEEE 1500, Analog Mixed-Signal test structures, DFT architecture, ATPG, EDA Tools, IEEE 1687 IJTAG, Siemens, Synopsys

boundary scan , Jtag, Perl, Python, Tcl, Sta, test coverage analysis, MBIST, Diagnosis, TAP Controller, Scan Insertion, Fault Models, Physical Design, ATPG, Scan Compression, LBIST, pattern generation, Mentor Tessent

Pcie, Perl, Verilog, Python, spyglass, VHDL, DDR memory controllers, CXL

Perl, Static Timing Analysis, Python, Tcl, Timing Closure STA, RTL-to-GDSII Execution, power analysis, Red Hawk, Programming Scripting, Fusion Compiler, Signal Integrity Analysis, Cross-Functional Collaboration, Tempus, LEC, Physical Formal Verification, primetime, Innovus, Calibre, PPA Optimization, EDA Tools, VCLP

Board Bring Up, Doors, Technical Documentation, Reports, Power Supply Design, antennas, chambers, EMI EMC qualification testing, Through Hole and SMD board assembly process, Power Electronics, PCB layout fabrication process, hardware design and development lifecycle process, DO-160, Procedures, EMI EMC instruments, qualification test plan, MIL-STD-461, DO-254 Process

power integrity , Shell, Perl, Python, Tcl, Ansys RedHawk, power grid optimization, Cadence Voltus, static and dynamic IR analysis

Usb, Uart, Spi, Jtag, Sata, hardware validation, DDR5 LPDDR memory subsystems, protocol analyzers, Power Tools, system debugging, Oscilloscopes, SoCs, Pcb Design, FPGAs, Signal Integrity, controlled impedance, AI-Enabled engineering, PCIe Gen4 5, I²C, PDN