About The Role

We are looking for an experienced and highly motivated SoC Architect to lead the architecture definition and technical direction for next-generation semiconductor products. The ideal candidate will have strong expertise in complex SoC architecture development, performance modeling, subsystem integration, and cross-functional collaboration across hardware, software, and system teams.

This role involves defining scalable and high-performance architectures for advanced compute platforms including AI, GPU, multimedia, networking, RISC-V or datacenter-class SoCs. This is a tech lead role. The ideal candidate must be willing to be an individual contributor while leading others.

What You'll Do

Define top-level SoC architecture and subsystem partitioning for complex semiconductor products.
Drive architecture tradeoff analysis for performance, power, area, bandwidth, latency, and scalability.
Develop and review system architecture specifications, interface definitions, and microarchitecture requirements.
Collaborate with RTL, verification, physical design, firmware, software, and system teams throughout the development cycle.
Lead performance modeling, workload analysis, and bottleneck identification using C/C++/SystemC or similar modeling environments.
Define memory hierarchy, NoC/interconnect strategy, coherency architecture, and cache structures.
Evaluate and integrate third-party IPs including CPU, GPU, NPU, PCIe, DDR/LPDDR, Ethernet, multimedia, and security subsystems.
Work closely with verification teams to define architectural test plans and validation strategies.
Support silicon bring-up, debug, performance tuning, and post-silicon optimization.
Contribute to long-term technology and product roadmap planning.

Required Qualifications

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
10+ years of experience in SoC architecture, ASIC development, or complex semiconductor system design.
Strong understanding of modern SoC architectures and subsystem integration.
Experience with one or more of the following:
CPU/GPU/NPU architectures
NoC/interconnect architectures
Cache coherency protocols (CHI/ACE/CXL)
High-speed interfaces (PCIe, UCIe, Ethernet)
Memory systems (DDR5, LPDDR5X, HBM)
Power/performance optimization
Strong knowledge of RTL development and verification methodologies.
Experience with architecture modeling and performance analysis tools.
Familiarity with firmware/software interaction in complex SoC systems.
Excellent problem-solving, communication, and leadership skills.

Preferred Qualifications

Experience with AI accelerator, GPU, networking, RISC-V or datacenter SoC architectures.
Experience with chiplet-based or multi-die architectures.
Familiarity with advanced process technologies and package integration.
Experience with emulation, FPGA prototyping, and system-level validation.
Knowledge of Linux drivers, runtime software, or system software architecture.
Prior technical leadership experience across cross-functional engineering teams.

Technical Skills

System architecture definition
C/C++/SystemC modeling
Performance analysis and simulation
RTL and microarchitecture understanding
AMBA/AXI/CHI protocols
PCIe/CXL/UCIe
Memory subsystem architecture
HW/SW co-design
Silicon bring-up and debugging

Director of SoC Architect