redhawk , Shell, Tcl, Verilog, PERL, Innovus, floorplan exploration and optimization, Starrcxt, place and route methodologies, physical implementation and analysis tools, Fusion Compiler, power integrity and reliability analysis, Calibre, VHDL, low power physical design flows and methodologies, timing and signal integrity analysis, metal-only ECO implementation, power grid planning and implementation, timing optimization and timing closure, placement and optimization, Clock Tree Synthesis

Physical Verification, foundry rule decks, Antenna Verification, ERC, Metal Fill Verification, DRC, PV signoff methodologies, LVS, Density Verification, advanced process technologies, PV automation scripts

Dsp, Performance Modeling, Cuda, Python, low-level performance optimization, fixed-point arithmetic, workload characterization, Bottleneck Analysis, Benchmarking, robotics systems, simd, memory hierarchy, VLIW, autonomous systems, sensor processing, HW SW co-design, multimodal perception, emerging physical AI workloads

clocking , Arm, Trace32, Multimedia, Microprocessors, Computer Architecture, interconnect safety, Synthesis, Security, ARM Debug, Ace, RTL design flow, Verilog RTL coding, RISC-V, APB, Axi, Reset, ATB, BUS Protocols, Chip Assembly, LINT, RTL signoff tools, Serial Interfaces, cdc, ARM CoreSight ETM, IP Integration, Arm Cortex-M A R processor-based SoC debug infrastructure, External Bus Interfaces, RDC, System modes