Physical Verification, foundry rule decks, Antenna Verification, ERC, Metal Fill Verification, DRC, PV signoff methodologies, LVS, Density Verification, advanced process technologies, PV automation scripts

System Verilog, Digital-analog interface requirements, RTL design and development, Linting, Mixed-signal design flows, RDC analysis, Coverage-driven design methodologies, Timing Constraints, Digital control logic, Synthesis and timing closure methodologies, RTL coding in Verilog, Low-power design techniques

static timing analysis, Verilog, Python, Tcl, SDC development, Tempus, Cadence Innovus, simulation methodologies, Rtl Design, transistor-level concepts, Genus, digital circuit operation, custom layout fundamentals, place-and-route, multi-clock designs, Synthesis, digital design fundamentals, floorplanning, Physical Verification, systemverilog, CDC concepts, Timing Constraints, Liberty timing models, characterization concepts

physical testing , test environments , Requirements Traceability, Test Cases, system integration, compliance documentation, verification strategies, Simulation, verification plans, Regulatory Compliance, Analysis, certification artifacts, ground testing, ground test setups, Flight Testing, Inspection