Perl scripting, Delay Faults, Pattern Simulation, Siemens Tessent, Transition Faults, Synopsys TestMAX, Pattern Generation, DFT Compiler, Scan Insertion, DFT implementation, DFT DRC violations, ATPG, Cadence Modus, Stuck-at Faults

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools