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At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you're designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

The Role

We are seeking a seasoned SoC PD lead with expertise in delivering high-quality physical design implementations that meet PPA and schedule targets, contribute to physical design innovation, influencing multiple programs and organizational decisions, meticulous about Power, Performance and Area while driving schedule and managing cost.

The Person

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

Key Responsibilities

Own end-to-end physical design for high-performance, low-power SoCs, including floorplanning, placement, clock tree synthesis, routing, and timing closure.
Define and optimize PnR strategies for advanced nodes (e.g., 5nm/3nm/2nm), balancing performance, power, and area (PPA).
Establish and drive sign-off criteria and waiver processes.
Introduce innovative techniques for congestion management, timing optimization, and power integrity.
Partner with RTL, architecture, CAD, and verification teams to resolve design challenges and ensure seamless integration.
Influence design partitioning, interface planning, and hierarchical strategies to meet aggressive schedules.
Anticipate schedule risks tied to ECO delivery and resource constraints; implement prefetch and compliance gates for ECO readiness.
Publish risk burndown reports and mitigation plans for tapeout-critical paths.
Lead technical reviews and provide consultative input to management on design trade-offs.
Work closely with Design teams for Area and Floorplan refinement, Timing targets, Pre-Si bug resolution and PPA sign-off.

Preferred Experience

15+ Years of experience in relevant domain.
Proficient in Working with various EDA tools. Innovus, Fusion compiler/ICCompiler2, Primetime etc.
Foundational experience in SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks & Resets.
Excellent communication, management, and presentation skills.
Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies

Academic Credentials

Bachelors or Masters degree in computer engineering/Electrical Engineering c

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available here.

This posting is for an existing vacancy.

SoC Physical Design Lead

SoC Physical Design Lead