Fpga, Vcs, Pcie, Ethernet, Xcelium, Emulation, Uvm, systemverilog, Dft, Questa, DDR5, DDR4

Shell, Perl, Python, Tcl, Cadence Xcelium, Mentor QuestaSim, PCI Express, Uvm, systemverilog, Synopsys VCS, Assertion-Based Verification, Constrained Random Verification, Functional Verification

Perl, Python, Tcl, Functional Coverage, Uvm, SVA, systemverilog, ASIC SoC Subsystem IP verification

Usb, DDR, Perl, Pcie, Ethernet, Python, Tcl, Uvm, coverage-driven verification, systemverilog, digital design RTL understanding, AMBA, MIPI, SVA

Verilog, systemverilog, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, VMM, random stimulus

Vcs, Xcelium, JasperGold, formal verification tools, assertion-based verification, Uvm, systemverilog, Questa, VC Formal, SVA, functional coverage

digital logic, Specman E, Debug, IP subsystem SoCs, Verification, AI ML accelerators, systemverilog, vector processing units

Perl, Python, Synopsys VCS, Cadence Xcelium, Uvm, systemverilog

Design-for-Debug (DFD) and Verification Debug, Verilog, Usb, Pcie, UVM-based Verification Environment Development, Verification Planning Execution, SoC Subsystem Verification, Testbench Development, Interconnect Verification, systemverilog, Functional Coverage, UFS, Axi, Assertions SVA, EMAC Ethernet, Coverage-driven Verification, AHB, AMBA ATB Protocols