Jasper, Perl, Python, Asic verification, verification methodologies, Synopsys Magellan, Uvm, systemverilog, Cadence IEV, VC Formal, functional coverage, SVA

Pcie, CHI, Ace, UVM methodology, UCIe, systemverilog, Axi, AMBA, RAS features, CXL, debugging skills, SVA

bandwidth management , Microprocessor Cores, Specman E, SoCs, standard IP components, systemverilog, hierarchical memory subsystems, constrained-random verification environments, Verification, interconnects, packet processing, congestion control, Debug

Shell, Perl, Verilog, Python, Tcl, UVM methodology, Cadence, systemverilog, Functional and code coverage, Simulation and debugging concepts, Verification tools from Synopsys, Siemens EDA

Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA

simvision , Verilog, Shell scripting, Python, RFIC, Analog, Tcl, Xcelium, Uvm, 6G, RNM, Spice, Functional Verification, SoC Verification, Cadence Tool, systemverilog, Spectre, 5G, behavioral modeling, Rf, Verisium, Verilog-AMS, AMS Verification, virtuoso, Mixed-Signal Verification