Shell, Perl, Verilog, Python, Tcl, LINT, cdc, PCI Express PCIe Gen4 Gen5 Gen6, systemverilog, Timing-aware RTL Development, ASIC RTL Design, Synthesis, RDC, Digital Logic Implementation, Microarchitecture, SoC Integration

Verilog, Cache, Soc Architecture, fabric coherence, memory compression, systemverilog, logic synthesis techniques, FPGA and emulation platforms, digital logic design principles, Synthesis, DRAM, FPGA design verification, assertion-based formal verification, RTL design concepts, Dft, low-power design techniques, power analysis

ASIC RTL Design, systemverilog, Micro-Architecture, Clock/Reset Design, Low-Power Design, UPF

Low power microarchitecture techniques, High performance low latency high bandwidth design techniques, Verilog RTL logic design, Knowledge of logic design principles including timing and power implications, Experience with simulators and waveform debug tools, Area and power-efficient complex RTL design

Uart, Spi, Verilog, I2c, LINT, cdc, MAS development, Sub-system design, SoC integration, ip design, Quality check flows, AMBA bus protocols, Axi, APB, RTL Coding, Medium complexity protocol, AHB, Microarchitecture