Jtag, Perl, Verilog, System Verilog, Python, Tcl, Mentor Questa, Cadence Xcelium, JasperGold, Uvm, multi-clock domain mixed signal designs, Root Cause Analysis, debugging of complex mixed signal designs, Synopsys VCS, APB, constraint-random test generation, CRI, IJTAG

Python, Tcl, Analog mixed-signal IC design, Verilog-AMS, AMS Designer, behavioral modeling, Cadence Virtuoso, Verification, systemverilog, Spectre