power integrity , Routing, Perl, Python, Tcl, Chip finishing, Metal fill, Clock Trees, Tapeout checks, Physical Verification, Sealring, Signal Integrity, RTL2GDS flow, Floorplans, Power Distribution Network, Physical Design, Timing Closure, Placement, Physical Sign off, Equivalence Check, Synthesis Constraints

Git, Bitbucket, Verilog, Visualstudio, Python, System C, Uvm, systemverilog

Usb, DDR, Pcie, Verilog, Ethernet, LINT, Sta, Synthesis, cdc, UCIe, systemverilog, spyglass, VHDL, formal checking, RDC, HBM

Unix, Perl, Linux, Shell scripting, Python, Tcl, Place Route Cadence Innovus, Physical Verification Calibre DRC LVS, IR EM Cadence Voltus RedHawk, STA Cadence Tempus

Fpga, Logic Design, Verilog, Uvm, Timing Constraints, TCL scripts, regression frameworks, Timing Analysis, Power product design, System-Verilog, RTL Coding, Functional Verification, Sta, micro-architecture, ATPG generation, formal verification, synthesis scripts, Synthesis, ABV, design constraints, Digital Verification, Scan Insertion

Spi, Uart, Verilog, Arm, System Verilog, I2c, Gpio, USB standards, Synopsys, ASIC design flow, Interconnect fabrics, Arteris fabrics, RTL Coding, Cadence, Scripting in Perl, Peripheral interface IPs, QSPI, I3C, System Verilog assertions, NoC architecture, Third-party IP integration, Axi