UNIX, Debugging, Verilog, Windows, System Verilog, Digital IP development, RTL Coding, Automated flows for generating RTL

Java, C, Python, SIMD vectorization, Cache-aware execution, Performance profiling, Parallel execution strategies, qemu, Benchmarking, Optimization

Perl, Python, Tcl, Skill, Calibre PVS, Cadence Virtuoso, High-voltage process technologies, IR drop, Physical verification tools, PEX, Reliability-aware layout, Antenna density, High-current routing, Layout methodology improvements, LVS, Parasitic control, Latch-up prevention, Electromigration, Noise isolation, Thermal effects, ERC, DRC, Extraction and reliability tools, Tape-out readiness, Guard rings

Perl, Python, Tcl, primetime, Cadence Innovus, EM analysis, Physical Verification, Signal Integrity, StarRC, Timing Closure, low-power design techniques, Synopsys ICC2

monte carlo , python, AI ML, Cadence Virtuoso, Spice Simulator