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Senior Staff VLSI Design Engineer (SystemC, Functional Modeling, C++ , Verification)

Sandisk
Bengaluru, India

Skills:

Git, Bitbucket, Verilog, Visualstudio, Python, System C, Uvm, systemverilog

Early Applicant

Senior Staff Design Verification Engineer

d-Matrix
Bengaluru, India

Skills:

IP SoC verification, ASIC-SoC design verification, systemverilog

Early Applicant

Senior Staff Design Verification Engineer

DMatrix
Bengaluru, India

Skills:

IP SoC verification, ASIC-SoC design verification, systemverilog

Early Applicant

Senior Staff Design Verification Engineer

Renesas Electronics
Bengaluru, India

Skills:

Fpga, Logic Design, Verilog, Uvm, Timing Constraints, TCL scripts, regression frameworks, Timing Analysis, Power product design, System-Verilog, RTL Coding, Functional Verification, Sta, micro-architecture, ATPG generation, formal verification, synthesis scripts, Synthesis, ABV, design constraints, Digital Verification, Scan Insertion

Early Applicant
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