conformal lec , Perl, Shell script, Tcl, DFT Insertion, Fusion Compiler, Conformal Low Power, Formality, VCLP tool, Tempus, primetime, Logic equivalence check, UPF Low power concepts, Physical Synthesis, Genus, pre-STA timing analysis, functional ECO flow, verifying constraints quality and completeness

Perl, Python, Tcl, primetime, constraint development, Fusion Compiler, low-power design methodologies, Timing Analysis, Cadence Genus, UPF-based flows, RTL synthesis, Synopsys Design Compiler, Timing Closure

Static timing analysis, design optimization, SDC constraints, Logic Synthesis, Timing ECOs, Clock-gating checks, CDC-related timing issues, UPF, ECO implementation, MMMC timing analysis, Timing Closure, Formal equivalence checking, CPF, Low-power design methodologies, PPA optimization, Physical-aware RTL-to-gate synthesis

synopsys primetime , Python Scripting, Design Compiler, SDC constraint authoring and management, Physical-aware synthesis flows, Fusion Compiler, Formality, Physical-Aware Synthesis, STA PrimeTime

Clp, automation, Scripting, LINT, prelayout STA, low power aspects, postlayout STA, Synthesis, cdc, SDC generation, demotion, SDC development, LEC, RTL Netlist based static checks, Dft, Timing Constraints, Timing Closure, Verification, promotion, equivalence checking