C, Python, constrained-random verification, Uvm, system-level test generation, Portable Stimulus, systemverilog

Tcl, Python, Perl, routing, signoff, ASIC design flow, PPA optimization, Timing Analysis, EDA Tools, Placement, Synthesis, Timing Closure, RTL-to-GDSII

embedded software programming , C, Python, Pcie, DDR, SoC Verification, Uvm, ARM-based SoCs, system-level test generation, systemverilog, Emulation, reusable verification libraries, virtual platforms, Portable Stimulus PSS, constrained-random verification, Perspec, post-silicon validation, verification methodology