System Verilog, Regression Analysis, bus protocols like AHB AXI, clock domain crossing designs, RTL verification in C System Verilog UVM, Uvm, low power verification methodology, PA GLS verification of DC and PD PG Netlist, Power Aware Verification, IP Integration testing, post-Si debug, verification environment and testbench components, Assertion for temporal logic testing, digital front end ASIC design verification, formal verification, Modem Wireless IP verification, bug-triage, Code Functional coverage, Cadence and Synopsys simulator tools, development test automation framework, scripting languages like Perl Python