Verilog, Sata, Python, Perl, Usb, Uvm, constrained random verification, functional coverage, PCI Express, VMM, systemverilog, DV methodologies

Usb, Perl, Verilog, Sata, Python, Testbench development using SystemVerilog, DV methodologies, PCI Express, Uvm, verification tools for simulation and debug, systemverilog, functional coverage based constrained random verification, VMM

PCIe Formal Verification Engineer, PCI Express, formal verification, FPV, SVA, SystemVerilog Assertions, Questa Formal

Perl, Python, Tcl, coverage analysis, PCIe Gen3, Simulation Tools, UVM-based testbenches

Nvme, Vcs, DDR, Pcie, Python, Uvm, Logic Analyzers, Waveform Viewers, protocol analyzers, UCIe, systemverilog, Questa, Modelsim